gsrd_7_1_2

所属分类VHDL/FPGA/Verilog
开发工具:VHDL
文件2018注册送白菜网:18253KB
下载次数:40
上传日期:2009-07-02 20:29:48
上 传 者开源就好了
说明:  xilinx下的Gbit级通行参考设计,已经过本人验证
(Gbit-class xilinx passage under the reference design, I have been to verify)

文件列表:[举报垃圾]
gsrd
....\downloads
....\.........\ml300_ll_gemac_tft
....\.........\..................\download.bit
....\.........\..................\linux.elf
....\.........\..................\treck.elf
....\.........\..................\xllgemac_tx_rx.elf
....\.........\..................\xmd.ini
....\.........\ml310_ll_gemac
....\.........\..............\download.bit
....\.........\..............\linux.elf
....\.........\..............\treck.elf
....\.........\..............\xllgemac_tx_rx.elf
....\.........\..............\xmd.ini
....\.........\ml403_ll_temac
....\.........\..............\download.bit
....\.........\..............\linux.elf
....\.........\..............\treck.elf
....\.........\..............\xlltemac_tx_rx.elf
....\.........\..............\xmd.ini
....\edk_libs
....\........\gsrd_lib
....\........\........\drivers
....\........\........\.......\gsrduartlite_v1_00_b
....\........\........\.......\....................\build
....\........\........\.......\....................\.....\vxworks5_4
....\........\........\.......\....................\.....\..........\xtag_csp_uartlite_v1_00_b.c
....\........\........\.......\....................\data
....\........\........\.......\....................\....\gsrduartlite_v2_1_0.mdd
....\........\........\.......\....................\....\gsrduartlite_v2_1_0.tcl
....\........\........\.......\....................\examples
....\........\........\.......\....................\........\xuartlite_intr_example.c
....\........\........\.......\....................\........\xuartlite_low_level_example.c
....\........\........\.......\....................\........\xuartlite_polled_example.c
....\........\........\.......\....................\src
....\........\........\.......\....................\...\Makefile
....\........\........\.......\....................\...\xuartlite.c
....\........\........\.......\....................\...\xuartlite.h
....\........\........\.......\....................\...\xuartlite_g.c
....\........\........\.......\....................\...\xuartlite_i.h
....\........\........\.......\....................\...\xuartlite_intr.c
....\........\........\.......\....................\...\xuartlite_io.h
....\........\........\.......\....................\...\xuartlite_l.c
....\........\........\.......\....................\...\xuartlite_l.h
....\........\........\.......\....................\...\xuartlite_selftest.c
....\........\........\.......\....................\...\xuartlite_stats.c
....\........\........\pcores
....\........\........\......\dcr2opb_bridge_v2_00_a
....\........\........\......\......................\data
....\........\........\......\......................\....\dcr2opb_bridge_v2_1_0.mpd
....\........\........\......\......................\....\dcr2opb_bridge_v2_1_0.pao
....\........\........\......\......................\hdl
....\........\........\......\......................\...\verilog
....\........\........\......\......................\...\.......\dcr2opb_bridge.v
....\........\........\......\dcr_dcm_phase_mod_v2_00_a
....\........\........\......\.........................\data
....\........\........\......\.........................\....\dcr_dcm_phase_mod_v2_1_0.mpd
....\........\........\......\.........................\....\dcr_dcm_phase_mod_v2_1_0.pao
....\........\........\......\.........................\hdl
....\........\........\......\.........................\...\verilog
....\........\........\......\.........................\...\.......\dcr_dcm_phase_mod.v
....\........\........\......\dcr_intc_v1_00_b
....\........\........\......\................\data
....\........\........\......\................\....\dcr_intc_v2_1_0.mpd
....\........\........\......\................\....\dcr_intc_v2_1_0.pao
....\........\........\......\................\hdl
....\........\........\......\................\...\vhdl
....\........\........\......\................\...\....\dcr_intc.vhd
....\........\........\......\................\...\....\dcr_intfc.vhd
....\........\........\......\ll_data_gen_v2_00_a
....\........\........\......\...................\data
....\........\........\......\...................\....\ll_data_gen_v2_1_0.mpd
....\........\........\......\...................\....\ll_data_gen_v2_1_0.pao
....\........\........\......\...................\hdl
....\........\........\......\...................\...\verilog
....\........\........\......\...................\...\.......\ll_data_gen.v
....\........\........\......\ll_tft_cntlr_v2_00_a
....\........\........\......\....................\data
....\........\........\......\....................\....\ll_tft_cntlr_v2_1_0.mpd
....\........\........\......\....................\....\ll_tft_cntlr_v2_1_0.pao
....\........\........\......\....................\hdl
....\........\........\......\....................\...\verilog
....\........\........\......\....................\...\.......\dcr_if.v
....\........\........\......\....................\...\.......\h_sync.v
....\........\........\......\....................\...\.......\ll_dst_if.v
....\........\........\......\....................\...\.......\ll_tft_cntlr.v
....\........\........\......\....................\...\.......\local_link_if.v
....\........\........\......\....................\...\.......\rgb_bram.v
....\........\........\......\....................\...\.......\tft_if.v
....\........\........\......\....................\...\.......\v_sync.v
....\........\........\......\plb_m1s1_v1_00_a
....\........\........\......\................\data
....\........\........\......\................\....\plb_m1s1_v2_1_0.mpd
....\........\........\......\................\....\plb_m1s1_v2_1_0.pao
....\........\........\......\................\....\plb_m1s1_v2_1_0.tcl
....\........\........\......\................\hdl
....\........\........\......\................\...\vhdl
....\........\........\......\................\...\....\plb_m1s1.vhd
....\........\........\sw_services
....\........\........\...........\treck_v1_00_a

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